Verification Group Manager
Texas 
Benefits - Full

Relocation Assistance Available - Yes

Bonus Eligible - Yes
Interview Travel Reimbursed - Yes

As an integral member of our product development team, you will lead a Verification Engineering group responsible for verification planning, test bench development, failure analysis and resolution, coverage analysis, digital/mixed-signal modeling, directed/constraint-random test generation and flow development.   You will also work closely with applications, product and test engineering to support silicon validation efforts.

The ideal candidates will have a MSEE or MSCS and 10 years of verification experience preferably in mixed signal products. Strong background with HDLs (e.g. Verilog, VHDL), HVLs (e.g. SystemVerilog/OVM, UVM, AVM, Vera, e) and assertions are required. The candidate must have solid scripting skills with Matlab, Perl, Python, Unix/Linux shell, TCL, and be able to write and debug analog behavioral models in Verilog, Verilog-A, and/or Verilog-AMS.  Knowledge of signal processing and power conversion are also a plus.  You must also be able to communicate complex technical concepts and posses the desire to be a key contributor to the growth of our division.