The Position
Senior Physical Design Engineer
Semiconductors
Engineering - Other Engineering

Full-time
United States - Texas 

You will be responsible for all aspects of physical implementation from RTL to GDS, including RTL synthesis, scan stitching, timing constraints creation, Power analysis, chip floor plan, clock distribution, full chip assembly, Timing driven Placement & Route, Static Timing Analysis, timing closure, ECO and tapeout. Interface with other design groups to ensure time to market and quality of results. You will also participate in design/architecture reviews, establishing & defining physical design methodologies and flow automation.

This company is a great place to work because:

We are located in the fun city of Austin and soon to move into a new downtown building. We have a great CEO and have lots of fun at work. We have Friday onsite Happy Hours and live music once a month onsite.

The Candidate
5+ to 7 years of experience
Minimum Education - Bachelor's Degree

The Ideal Candidate

This position requires a BSEE/MSEE and 5+ years industry experience in a Logic design or Physical Design position. Candidate should preferably have strong knowledge of RTL design and must be familiar with RTL compiler/Design Compiler, ICC/SOC Encounter, Primetime, Conformal LEC, and ATPG. Ideal candidate will also have working knowledge of scan insertion, and ATPG. Must have good communication, teamwork, and debug/analysis skills for designs, library and technology files.