Senior Digital Design Methodology Engineer
TX

Benefits - Full

Relocation Assistance Available - Possible for the ideal candidate

Join a team responsible for defining the future of chip development methodologies for the entire company. The applicant will be responsible for development, deployment, and support of the mixed-signal methodology with an emphasis on front end design and verification. Tasks include defining and documenting work flows, developing internal tools, evaluating external tools and providing training. The applicant will be a key contributor to driving process improvements that raise the level of quality and efficiency of the entire organization. Applicants must be able to work independently and in small teams, have initiative and self-motivation.  Excellent verbal and written communication skills are required. The ideal candidate will possess strong backgrounds in both IC design and software development.

Minimum qualifications

Must have a Bachelors or Masters in Electrical or Computer Engineering and 5 to 15 years experience in CAD/digital design/verification.

Must be familiar with RTL design and verification flows and industry standard EDA tools

Experience with coding in HDL languages such as Verilog, SystemVerilog or VHDL

Experience with Unix operating system and scripting languages including Perl, Python, TCL, C-Shell

Experience with version control tools such as Subversion, Perforce or git

Preferred Qualifications:

Experience with constrained random verification methodologies including UVM/OVM, SystemVerilog, functional coverage and assertions

Experience with Cadence Virtuoso and SKILL a plus

Experience or training in AGILE Project Management a plus

Experience in web development languages including JavaScript, XML, HTML, CSS a plus

5+ to 7 years of experience
Minimum Education - Bachelor's Degree

Willingness to Travel - Occasionally