IP Integration Engineer up to 110k base
Texas 

Benefits - Full

Relocation Assistance Available - Yes

Bonus Eligible - Yes
Interview Travel Reimbursed - Yes

Description

Involved in re-package and distribution of 3rd party IP as well as development, characterization, view-generation, maintenance, qualification and distribution of in-house IP including stdcells, memories and IO. All tasks require a wide range of analog and digital design tools as well as a script development for automation purpose.  Responsibilities include IP characterization; View-generation and re-packaging of 3rd party IP; development of view-generation scripts; validation of third-party IP.

Required Education:

MS in Electrical or Computer Engineering is required.

Required Qualifications:

•Must have understanding of CMOS devices including fabrication process

•Must have understanding of VLSI and APR flow

•Must have understanding of IP design (standard cells, IO's, or memory)

•Must have extensive experience with spice simulations

•Must have experience with Verilog coding

•Must have experience AOCV view generation

•Experience in geometries at 28nm or below preferred

•Experience in Synopsys timing and power modeling is preferred

•Should have fundamental understanding of noise modeling

•Experience in layout is preferred

•Must have experience in perl script coding (tcl and skill coding nice to have)

•Must have understanding of a typical analog design flow and tools for schematic entry, simulation and layout

•Must have understanding of a typical RTL-GDS design flow (digital tools)

•Familiar with industry RTL compiler is preferred

•Familiar with industry place and route tool is preferred

•Familiar with running DRC and LVS

•Experience with version control tools is preferred

•Excellent written and verbal communication skills

5+ to 7 years of experience

Minimum Education - Bachelor's Degree