DFT Manager Design For Test

Join a DFT team working on industry leading mixed-signal SoCs for consumer mobile audio markets.

Responsibilities

         Participate and drive full chip DFT architecture and feature definitions

         Responsible for DFT specification generation and review

         Responsible for implementing key DFT functions and verifying them including Test mode controllers, Clock & reset control, At-speed test logic control using PLLs, Scan insertion, On-chip test pattern compression insertion, Boundary scan and Memory BIST & Memory Redundancy

         Generation of DFT related timing constraints

         Work with physical design team on timing closure

         Simulations to confirm correct functionality

         Includes RTL, annotated and zero delay gate level

         Work closely with IC Design Product & Test engineering to ensure timely delivery of robust test patterns

         Participate in ATE bring-up and debug of DFT patterns with test engineers

         Resolve test pattern and coverage issues

         Support test engineering and operations through qualification, burn-in and production

         Support failure analysis and fault isolation of pattern failures for ongoing yield support

         Developing, enhancing and maintaining DFT related scripts as necessary

         Deployment of DFT methodologies for continuous improvement


Required Knowledge, Skills and Experience

         Possess strong hands on working knowledge on ASIC DFT design and verification

         Expertise in industry standard EDA tools for DFT such as DFTAdvisor, Fastscan, TestKompress, Tetramax, Test Compiler etc

         Understanding of ATE and test engineering

         IEEE JTAG standards e.g. 1149.1/P1687 IJTAG

         Experience with tool and flow automation

         Good communication, problem solving, planning and organizational skills

         Good English (written and verbal)

         Solid team player

 

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